?2006 by catalyst semiconductor, inc. characteristics subject to change without notice 1 doc. no. 25089, rev. b 5v and 3.3v supply monitor, watchdog timer, manual reset, with active high & low resets cat1232lp/cat1832 features selectable reset voltage tolerance cat1232lp for 5v supply cat1832 for 3.3v supply selectable watchdog period: 150ms, 600ms or 1.2 sec two reset outputs active high, push-pull reset output active low, open-drain reset output (cat1232lp) active low, push-pull reset output (cat1832) debounced manual push-button reset compact soic and msop packages description the cat1232lp and cat1832 microprocessor supervisors can halt and restart a ?ung-up?or ?talled microprocessor, restart a microprocessor after a power failure, and debounce a manual/push-button micro- processor reset switch. the devices are drop in replacements for the maxim/dallas semiconductor ds1232lp and ds1832 supervisors precision reference and comparator circuits monitor the 5v or 3.3v system power supply voltage, v cc . during power-up or when the power supply falls outside selectable tolerance limits, both the reset and reset become active. after the power supply voltage rises above the reset threshold voltage, the reset signals remain active for a minimum of 250ms, allowing the power supply and system processor to stabilize. the trip-point tolerance input, tol, selects the trip level tolerance to be either 5% or 10% for the cat1232lp 5v supply and 10% or 20% for the cat1832 3.3v supply. each device has a push-pull, active high reset output. the cat1232lp also has an open drain, active low reset output while the cat1832 also has a push-pull, active low reset output. a debounced manual reset input activates the reset outputs and holds them active for a minimum period of 250ms after being released. also included is a watchdog timer to reset a microprocessor that has stopped due to a software or hardware failure. three watchdog time-out periods are selectable: 150ms, 600ms and 1.2sec. if the st input is not strobed low before the watchdog time out period expires, the reset signals become active for a minimum of 250ms. applications microprocessor systems portable equipment controllers single board computers instrumentations telecommunications functional diagram st reset pbrst 40k ? tol v cc + reference vcc reset td push button debounce watchdog timebase selection reset & watchdog timer (cat1232lp) watchdog transition detector reset (cat1832) tolerance selection
2 cat1232lp/cat1832 doc. no. 25089, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice ordering information pin configuration pin description v cc st reset reset 8-lead soic/msop/dip 1 2 3 4 8 7 6 5 pbrst td tol gnd 16-lead soic 8 gnd 7 nc 6 tol 5 nc 4 td 3 nc 2 pbrst 1 nc 9 reset 10 nc 11 reset 12 nc 13 st 14 nc 15 v cc 16 nc r e b m u n n i p e g a k c a p d a e l - 8 r e b m u n n i p e g a k c a p d a e l - 6 1e m a nn o i t c n u f 12 t s r b p t u p n i t e s e r n o t t u b h s u p l a u n a m d e c n u o b e d 24d t: n o i t c e l e s y a l e d e m i t l a c i p y t g o d h c t a w t ) a d t d n g = d t r o f s m 0 5 1 = t ) b d t n e p o = d t r o f s m 0 0 6 = t ) c d t v = d t r o f s m 0 0 2 1 = c c 36l o tv = l o t ( % 0 1 r o ) d n g = l o t ( % 5 s t c e l e s l o t p l 2 3 2 1 t a c c c p i r t ) = l o t % 0 2 r o ) d n g = l o t ( % 0 1 s t c e l e s l o t 2 3 8 1 t a c . e c n a r e l o t t n i o p v c c . e c n a r e l o t t n i o p p i r t ) 48d n gd n u o r g 59t e s e re v i t c a s i t e s e r . t u p t u o t e s e r h g i h e v i t c a v f i . 1 c c t n i o p p i r t e g a t l o v t e s e r e h t w o l e b s l l a f f i . 2 t s r b p w o l s i f i . 3 t s . s e r i p x e d t y b t e s d o i r e p t u o e m i t e h t e r o f e b w o l d e b o r t s t o n s i . p u - r e w o p g n i r u d . 4 61 1 t e s e r ) t e s e r e e s ( . t u p t u o t e s e r w o l e v i t c a 73 1 t s t u p n i e b o r t s 85 1v c c y l p p u s r e w o p , 2 1 , 0 1 , 7 , 5 . 3 , 1 6 1 , 4 1 c nn o i t c e n n o c l a n r e t n i o n d a e l e t a l p r e d l o s h s i n i f d a e l n s n e e r g h s i n i f d a e l u a d p i n n e e r g h s i n i f t r a p g n i r e d r o r e b m u n t r a p g n i r e d r o r e b m u n t r a p g n i r e d r o r e b m u ne g a k c a p r e p s t r a p e b u t r e p s t r a p l e e r e z i s l e e r ) h c n i ( p p l 2 3 2 1 t a cl p l 2 3 2 1 t a cg - l p l 2 3 2 1 t a cp i d , d a e l - 80 5 j p l 2 3 2 1 t a cw p l 2 3 2 1 t a cg - w p l 2 3 2 1 t a cc i o s , d a e l - 6 17 4 s p l 2 3 2 1 t a cv p l 2 3 2 1 t a cg - v p l 2 3 2 1 t a cc i o s , d a e l - 80 0 1 r p l 2 3 2 1 t a cz p l 2 3 2 1 t a cg - z p l 2 3 2 1 t a cp o s m0 0 1 3 1 t - j p l 2 3 2 1 t a c3 1 t - w p l 2 3 2 1 t a c2 t g - w p l 2 3 2 1 t a cc i o s , d a e l - 6 1 0 0 0 , 23 1 3 1 t - s p l 2 3 2 1 t a c3 1 t - v p l 2 3 2 1 t a c2 t g - v p l 2 3 2 1 t a cc i o s , d a e l - 8 0 0 0 , 23 1 3 1 t - r p l 2 3 2 1 t a c3 1 t - z p l 2 3 2 1 t a c5 2 t g - z g p l 2 3 2 1 t a cp o s m 0 0 5 , 23 1 p 2 3 8 1 t a cl 2 3 8 1 t a cg - l 2 3 8 1 t a cp i d , d a e l - 80 5 s 2 3 8 1 t a cv 2 3 8 1 t a cg - w 2 3 8 1 t a cc i o s , d a e l - 80 0 1 r 2 3 8 1 t a cz 2 3 8 1 t a cg - z 2 3 8 1 t a cp o s m0 0 1 3 1 t - s 2 3 8 1 t a c3 1 t - v 2 3 8 1 t a c2 t g - w 2 3 8 1 t a cc i o s , d a e l - 8 0 0 0 , 23 1 3 1 t - r 2 3 8 1 t a c3 1 t - z 2 3 8 1 t a c5 2 t g - z 2 3 8 1 t a cp o s m 0 0 5 , 23 1 the -g nipdau lead finish is only available on the green packager versions of this device.
3 cat1232lp/cat1832 doc. no. 25089, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice electrical characteristics unless otherwise stated, 1.0v v cc 5.5v and over the operating temperature range of -40 c to +85 c. all voltages are referenced to ground. absolute maximum ratings* voltage on v cc ....................................... -0.5v to 7.0v voltage on st and td ................. -0.5v to v cc + 0.5v voltage on pbrst , reset and reset ............................ -0.5v to v cc + 0.5v notes: (1) pbrst is internally pulled high to v cc through a nominal 40k ? resistor (r pu ). (2) reset is an open drain output on the cat1232lp. (3) reset remains within 0.5v of v cc on power-down until v cc falls below 2v. reset remains within 0.5v of ground on power-down until v cc falls below 2.0v. maximum junction temperature ...................... 125 c storage temperature range ............ -65 c to +150 c lead soldering temperature (10 sec) .............. 300 c operating temperature range ........... -40 c to +85 c l o b m y sr e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u v c c e g a t l o v y l p p u s0 . 15 . 5v i 1 c c t n e r r u c y l p p u s v c c p l 2 3 2 1 t a c , v 5 . 5 =5 30 5 a v c c 2 3 8 1 t a c , v 6 . 3 =0 25 3 v h i t s d n a t s r b p l e v e l h g i h t u p n i ) 5 ( 2 v c c v 3 . 0 +v ) 6 ( v c c v 4 . 0 - v l i t s d n a t s r b p l e v e l w o l t u p n i v c c p l 2 3 2 1 t a c , v 5 . 5 =3 . 0 8 . 0 v v c c 2 3 8 1 t a c , v 6 . 3 =5 . 0 v p t c c v c c ) d n g = l o t ( t n i o p p i r tp l 2 3 2 1 t a c0 5 . 42 6 . 44 7 . 4v v p t c c v c c v = l o t ( t n i o p p i r t c c )p l 2 3 2 1 t a c5 2 . 47 3 . 49 4 . 4v v p t c c v c c ) d n g = l o t ( t n i o p p i r t2 3 8 1 t a c0 8 . 28 8 . 27 9 . 2v v p t c c v c c v = l o t ( t n i o p p i r t c c )2 3 8 1 t a c7 4 . 25 5 . 24 6 . 2v t d t d o i r e p t u o - e m i t g o d h c t a wd n g = d t5 . 2 60 5 10 5 2s m t d t d o i r e p t u o - e m i t g o d h c t a wv = d t c c 0 0 50 0 2 10 0 0 2s m t d t d o i r e p t u o - e m i t g o d h c t a wg n i t a o l f d t0 5 20 0 60 0 0 1s m v h o e g a t l o v t u p t u oa 0 0 5 = i ) 3 ( v c c v 5 . 0 -v c c v 1 . 0 -v i h o t n e r r u c t u p t u ov 4 . 2 = t u p t u o ) 2 ( 0 5 3 a i l o t n e r r u c t u p t u o, v 4 . 0 = t u p t u o0 1a m i l i e g a k a e l t u p n i ) 1 ( 0 . 1 0 . 1a r u p r o t s i s e r p u - l l u p l a n r e t n i ) 1 ( 2 30 45 5k ? c n i e c n a t i c a p a c t u p n i 5f p c t u o e c n a t i c a p a c t u p t u o 7f p t b p t s r b p t e s e r l a u n a m e m i t w o l m u m i n i m t s r b p v = l i 0 2s m t t s r e m i t e v i t c a t e s e r0 5 20 0 60 0 0 1s m t t s t s h t d i w e s l u p ) 4 ( 0 2s n t d p r v c c o t t c e t e d l i a f r o t e s e r t e s e r 58s t f v c c e t a r w e l s0 2s t y l d p t s r b p o t w o l e l b a t s d n a t e s e r t e s e r e v i t c a 0 2s m t u p r v c c r o t e s e r o t t c e t e d t e s e r e v i t c a n i t e s i r s 5 =0 5 20 0 60 0 0 1s m t r v c c e t a r w e l sv 5 7 . 4 o t v 5 2 . 40 s n (4) must not exceed the minimum watchdog time-out period (t td ). the watchdog circuit cannot be disabled. to avoid a reset, st must be strobed. (5) measured with v cc 2.7v. (6) measured with v cc < 2.7v.
4 cat1232lp/cat1832 doc. no. 25089, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice typical characteristics for the cat1232lp, v cc = 5v and t amb = 25 c unless otherwise stated. threshold voltage vs. temperature (10% tol) threshold voltage vs. temperature (5% tol) supply current vs. temperature reset active time vs. temperature reset active time waveform transient response 4.610 4.615 4.620 4.625 4.630 -50 0 50 100 temperature (?) threshold voltage (v) tol = gnd (5%) 4.430 4.435 4.440 4.445 4.450 -50 0 50 100 temperature ( c) threshold voltage (v ) tol = vcc (10%) 0 10 20 30 40 -50 0 50 100 temperature ( c) supply current ( a) vcc = 4.5v vcc = 5.5v 300 400 500 600 700 800 -50 0 50 100 temperature ( c) reset active time (ms) vcc = 5.5v vcc = 4.5v td = open
5 cat1232lp/cat1832 doc. no. 25089, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice application information supply voltage monitor reset signal polarity and output stage structure reset is an active low signal. it is developed with an open drain driver in the cat1232lp. a pull-up resistor is required, typical values are 10k ? to 50k ? . the cat1832 uses a cmos push-pull output stage for the reset . reset is an active high signal developed by a cmos push-pull output stage and is the logical opposite to reset . trip point tolerance selection the tol input is used to select the v cc trip point threshold. this selection is made connecting the tol input to ground or v cc . connecting tol to ground makes the v cc trip threshold 4.62v for the cat1232lp and 2.88v for the cat1832. connecting tol to vcc makes the vcc trip threshold 4.37v for the cat1232lp and 2.55v for the cat1832. after v cc has risen above the trip point set by tol, reset and reset remain active for a minimum time period of 250ms. on power-down, once v cc falls below the reset threshold the reset outputs will remain active and are guaranteed valid down to a v cc level of 1.0v. e c n a r e l o t t c e l e s e g a t l o v t n i o p p i r t e c n a r e l o t ) v ( e g a t l o v t n i o p p i r t n i ml a n i m o nx a m p l 2 3 2 1 t a c v = l o t c c % 0 15 2 . 47 3 . 49 4 . 4 p l 2 3 2 1 t a c d n g = l o t % 50 5 . 42 6 . 44 7 . 4 2 3 8 1 t a c v = l o t c c % 0 27 4 . 25 5 . 24 6 . 2 2 3 8 1 t a c = l o td n g % 0 10 8 . 28 8 . 27 9 . 2 figure 1. timing diagram: power up figure 2. timing diagram: power down v cctp(max) v cctp v cctp(min) v cc rese t rese t t r t rpu v oh v ol v cctp(max) v cctp v cctp(min) v cc reset reset t f v oh v ol t rpd manual reset operation push-button input, pbrst , allows the user to issue reset signals. the pushbutton input is debounced and is pulled high through an internal 40k ? resistor. when pbrst is held low for the minimum time of 20 ms, both resets become active and remain active for a minimum time period of 250ms after pbrst returns high. no external pull-up resistor is required, since pbrst is pulled high by an internal 40k ? resistor. pbrst can be driven from a ttl or cmos logic line or short-ed to ground with a mechanical switch.
6 cat1232lp/cat1832 doc. no. 25089, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice watchdog timer and st st st st st input a watchdog timer stops and restarts a microprocessor that has stopped proper operation or become hung . the watchdog performs this function by monitoring the st input. after the reset outputs go inactive the st input must be strobed with a high-to-low signal transition prior to the minimum watchdog timeout period. however if the st input is not strobed with a high-to-low signal transi- tion prior to a watchdog timeout the reset outputs will become active for t rst reseting and restarting the microprocessor. once the resets return to the inactive state the watchdog timer restarts the process. the td input allows the user to select from three predetermined watchdog timeout periods. always use the minimum timeout period to determine the required frequency of st high-to-low transitions and the maxi- mum to determine the time prior to the reset outputs becoming active. st pulse widths must be 20ns or greater. the watchdog timer cannot be disabled. it must be strobed with a high-to-low signal transition to avoid a watchdog timeout and subsequent reset. figure 6. timing diagram: pushbutton reset v ih v il v oh v ol reset reset pbrst t pdly t pb t rst reset reset st valid strobe valid strobe invalid strobe t rst t st note: st is ignored whenever a reset is active. t td (min) t td (min) figure 4. cat1832 application circuit: pushbutton reset figure 7. timing diagram: strobe input figure 5. cat1232lp application circuit: watchdog timer pbrst 3.3v 1 v cc td 2 st tol cat1832 p 3 4 reset gnd 8 7 6 5 reset reset i/o pbrst 5v 1 10k v cc td 2 st tol cat1232lp p decoder 3 4 reset gnd 8 7 6 5 reset mreq address bus reset e g a t l o v d t l e v e l ) s m ( d o i r e p t u o - e m i t g o d h c t a w n i ml a n i m o nx a m d n g5 . 2 60 5 10 5 2 g n i t a o l f0 5 20 0 60 0 0 1 v c c 0 0 50 0 2 10 0 0 2
7 cat1232lp/cat1832 doc. no. 25089, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice package mechanical 16-lead wide body soic (300mil) notes: 1. complies with jedec publication 95 ms-013 dimensions; however, some dimensions may be more stringent. 2. all linear dimensions are in inches and parenthetically in millimeters. 0.2914 (7.40) 0.2992 (7.60) 0.394 (10.00) 0.419 (10.65) 0.0926 (2.35) 0.1043 (2.65) 0.0040 (0.10) 0.0118 (0.30) 0.050 (1.27) bsc 0.013 (0.33) 0.020 (0.51) 0 8 0.0091 (0.23) 0.0125 (0.32) 0.010 (0.25) 0.029 (0.75) x 45 0.016 (0.40) 0.050 (1.27) 0.3977 (10.10) 0.4133 (10.50) 8-lead dip (300mil) 0.180 (4.57) max 0.015 (0.38) 0.100 (2.54) bsc 0.014 (0.36) 0.022 (0.56) 0.245 (6.17) 0.295 (7.49) 0.045 (1.14) 0.060 (1.52) 0.110 (2.79) 0.150 (3.81) 0.120 (3.05) 0.150 (3.81) 0.300 (7.62) 0.325 (8.26) 0.310 (7.87) 0.380 (9.65) 0.355 (9.02) 0.400 (10.16)
8 cat1232lp/cat1832 doc. no. 25089, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice package mechanical 8-lead msop 0.0150 0.0110 0.38 0.28 0.1970 0.1890 5.00 4.80 s 0.0256 [0.65] bsc 0.1220 0.1142 3.10 2.90 0.0433 [1.10] max. 0.039 [0.10] max. s 0.0059 0.0020 0.15 0.05 s 0.0374 0.0295 0.95 0.75 0.0276 0.0157 0.70 0.40 0.1220 0.1142 3.10 2.90 0 ? - 6 ? 8-lead narrow body soic (150mil) 0.1497 (3.90) 0.1574 (4.00) 0.2294 (5.90) 0.2440 (6.20) 0.0926 (2.35) 0.1043 (2.65) 0.0040 (0.10) 0.0099 (0.25) 0.050 (1.27) bsc 0.013 (0.33) 0.020 (0.51) 0 8 0.0075 (0.19) 0.0099 (0.25) 0.0099 (0.25) 0.0196 (0.75) x 45 0.016 (0.40) 0.050 (1.27) 0.1990 (4.90) 0.1969 (5.00)
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 25089 revison: b issue date: 03/27/06 revision history e t a dn o i s i v e rs t n e m m o c 5 0 0 2 / 3 1 / 6 00 0e u s s i l a i t i n i 5 0 0 2 / 6 2 / 7 0a s c i t s i r e t c a r a h c l a c i r t c e l e e t a d p u s c i t s i r e t c a r a h c l a c i p y t d d a 6 0 0 2 / 7 2 / 3 0b e l t i t t n e m u c o d e t a d p u n o i t a m r o f n i g n i r e d r o e t a d p u
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